From: Steven Kao Date: Mon, 23 Oct 2017 10:22:09 +0000 (+0800) Subject: Tegra: rename secure scratch register macros X-Git-Url: http://git.openwrt.org/%22https:/collectd.org//%22/%22https:/collectd.org/%22?a=commitdiff_plain;h=601a8e549544ea85f478f43b68c4afdc3430a9e7;p=project%2Fbcm63xx%2Fatf.git Tegra: rename secure scratch register macros This patch renames all the secure scratch registers to reflect their usage. This is a list of all the macros being renamed: - SECURE_SCRATCH_RSV1_* -> SCRATCH_RESET_VECTOR_* - SECURE_SCRATCH_RSV6 -> SCRATCH_SECURE_BOOTP_FCFG - SECURE_SCRATCH_RSV11_* -> SCRATCH_SMMU_TABLE_ADDR_* - SECURE_SCRATCH_RSV53_* -> SCRATCH_BOOT_PARAMS_ADDR_* - SECURE_SCRATCH_RSV55_* -> SCRATCH_TZDRAM_ADDR_* NOTE: Future SoCs will have to define these macros to keep the drivers functioning. Change-Id: Ib3ba40dd32e77b92b47825f19c420e6fdfa8b987 Signed-off-by: Steven Kao --- diff --git a/plat/nvidia/tegra/common/drivers/smmu/smmu.c b/plat/nvidia/tegra/common/drivers/smmu/smmu.c index 789f11c8..333d7d16 100644 --- a/plat/nvidia/tegra/common/drivers/smmu/smmu.c +++ b/plat/nvidia/tegra/common/drivers/smmu/smmu.c @@ -123,9 +123,9 @@ void tegra_smmu_save_context(uint64_t smmu_ctx_addr) (sizeof(smmu_regs_t) * num_entries)); /* save the SMMU table address */ - mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV11_LO, + mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SMMU_TABLE_ADDR_LO, (uint32_t)smmu_ctx_addr); - mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV11_HI, + mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SMMU_TABLE_ADDR_HI, (uint32_t)(smmu_ctx_addr >> 32)); } diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h index 8dee5070..231f93ac 100644 --- a/plat/nvidia/tegra/include/t186/tegra_def.h +++ b/plat/nvidia/tegra/include/t186/tegra_def.h @@ -239,6 +239,16 @@ #define SECURE_SCRATCH_RSV55_LO U(0x808) #define SECURE_SCRATCH_RSV55_HI U(0x80C) +#define SCRATCH_RESET_VECTOR_LO SECURE_SCRATCH_RSV1_LO +#define SCRATCH_RESET_VECTOR_HI SECURE_SCRATCH_RSV1_HI +#define SCRATCH_SECURE_BOOTP_FCFG SECURE_SCRATCH_RSV6 +#define SCRATCH_SMMU_TABLE_ADDR_LO SECURE_SCRATCH_RSV11_LO +#define SCRATCH_SMMU_TABLE_ADDR_HI SECURE_SCRATCH_RSV11_HI +#define SCRATCH_BL31_PARAMS_ADDR SECURE_SCRATCH_RSV53_LO +#define SCRATCH_BL31_PLAT_PARAMS_ADDR SECURE_SCRATCH_RSV53_HI +#define SCRATCH_TZDRAM_ADDR_LO SECURE_SCRATCH_RSV55_LO +#define SCRATCH_TZDRAM_ADDR_HI SECURE_SCRATCH_RSV55_HI + /******************************************************************************* * Tegra Memory Mapped Control Register Access constants ******************************************************************************/ diff --git a/plat/nvidia/tegra/soc/t186/plat_memctrl.c b/plat/nvidia/tegra/soc/t186/plat_memctrl.c index a2a81554..71904a8f 100644 --- a/plat/nvidia/tegra/soc/t186/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t186/plat_memctrl.c @@ -561,8 +561,8 @@ void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes) */ val = tegra_mc_read_32(MC_SECURITY_CFG1_0) & MC_SECURITY_SIZE_MB_MASK; val |= tegra_mc_read_32(MC_SECURITY_CFG0_0) & MC_SECURITY_BOM_MASK; - mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV55_LO, val); + mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_TZDRAM_ADDR_LO, val); val = tegra_mc_read_32(MC_SECURITY_CFG3_0) & MC_SECURITY_BOM_HI_MASK; - mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV55_HI, val); + mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_TZDRAM_ADDR_HI, val); } diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c index e0b5d2b9..5d3cdfaf 100644 --- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c @@ -123,7 +123,7 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) /* save 'Secure Boot' Processor Feature Config Register */ val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG); - mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV6, val); + mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_BOOTP_FCFG, val); /* save SMMU context to TZDRAM */ smmu_ctx_base = params_from_bl2->tzdram_base + diff --git a/plat/nvidia/tegra/soc/t186/plat_secondary.c b/plat/nvidia/tegra/soc/t186/plat_secondary.c index 19ca4fd0..16508093 100644 --- a/plat/nvidia/tegra/soc/t186/plat_secondary.c +++ b/plat/nvidia/tegra/soc/t186/plat_secondary.c @@ -56,9 +56,9 @@ void plat_secondary_setup(void) mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high); /* save reset vector to be used during SYSTEM_SUSPEND exit */ - mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_RSV1_SCRATCH_0, + mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO, addr_low); - mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_RSV1_SCRATCH_1, + mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI, addr_high); /* update reset vector address to the CCPLEX */ diff --git a/plat/nvidia/tegra/soc/t186/plat_setup.c b/plat/nvidia/tegra/soc/t186/plat_setup.c index bd6d7647..fd109e56 100644 --- a/plat/nvidia/tegra/soc/t186/plat_setup.c +++ b/plat/nvidia/tegra/soc/t186/plat_setup.c @@ -211,7 +211,7 @@ struct tegra_bl31_params *plat_get_bl31_params(void) { uint32_t val; - val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO); + val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_ADDR); return (struct tegra_bl31_params *)(uintptr_t)val; } @@ -223,7 +223,7 @@ plat_params_from_bl2_t *plat_get_bl31_plat_params(void) { uint32_t val; - val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI); + val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_ADDR); return (plat_params_from_bl2_t *)(uintptr_t)val; }